Sciweavers

376 search results - page 55 / 76
» Self-Assembled Circuit Patterns
Sort
View
ISVLSI
2008
IEEE
136views VLSI» more  ISVLSI 2008»
14 years 1 months ago
A Real Case of Significant Scan Test Cost Reduction
With the advent of nanometer technologies, the design size of integrated circuits is getting larger and the operation speed is getting faster. As a consequence, test cost is becom...
Selina Sha, Bruce Swanson
DATE
2007
IEEE
56views Hardware» more  DATE 2007»
14 years 1 months ago
Unknown blocking scheme for low control data volume and high observability
This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and a...
Seongmoon Wang, Wenlong Wei, Srimat T. Chakradhar
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
14 years 1 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...
ASPDAC
2006
ACM
100views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Generation of shorter sequences for high resolution error diagnosis using sequential SAT
Commonly used pattern sources in simulation-based verification include random, guided random, or design verification patterns. Although these patterns may help bring the design ...
Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moo...
ISCAS
2005
IEEE
130views Hardware» more  ISCAS 2005»
14 years 1 months ago
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
Inductance effects of on-chip interconnects have become more and more significant in today’s high-speed digital circuits, especially for global interconnects such as signal buse...
Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang