605 search results - page 6 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
EUROPAR
1999
Springer
13 years 11 months ago
1999
Springer
Growing demand for high performance in embedded systems is creating new opportunities for Instruction-Level Parallelism ILP techniques that are traditionally used in high perform...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
DAC
1999
ACM
14 years 8 months ago
1999
ACM
It is generally believed that there will be little more variety in CPU architectures, and thus the design of Instruction-set Architectures (ISAs) will have no role in the future o...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
DAC
2009
ACM
13 years 8 months ago
2009
ACM
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...