385 search results - page 29 / 77 » Semi-automatic Distributed Synthesis |
ISQED
2007
IEEE
14 years 4 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
DAC
2004
ACM
14 years 10 months ago
2004
ACM
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
ISQED
2007
IEEE
14 years 4 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
TASLP
2010
13 years 8 months ago
2010
—The synthesis of sound based on physical models of 2-D percussion instruments is problematic and has been approached only infrequently in the literature. Beyond the computationa...
ICCAD
2003
IEEE
14 years 6 months ago
2003
IEEE
In this paper, we present a reduced order inodeling methodology, based on the utilization of optimal non-uniform grids generated by Gaussian spectral rules, for the direct passive...