19 search results - page 3 / 4 » Sensitivity Analysis of a Cluster-Based Interconnect Model f... |
IOLTS
2003
IEEE
14 years 18 days ago
2003
IEEE
On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay v...
DATE
2002
IEEE
14 years 9 days ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
ISPD
2003
ACM
14 years 17 days ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...