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» Sequential Circuits for Relational Analysis
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ICCD
2001
IEEE
119views Hardware» more  ICCD 2001»
14 years 6 months ago
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...
Serdar Tasiran, Farzan Fallah, David G. Chinnery, ...
ICCAD
1997
IEEE
112views Hardware» more  ICCAD 1997»
14 years 1 months ago
Circuit optimization via adjoint Lagrangians
The circuit tuning problem is best approached by means of gradient-based nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the o...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
14 years 1 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
FPL
2004
Springer
94views Hardware» more  FPL 2004»
14 years 3 months ago
Evaluating Fault Emulation on FPGA
Abstract. We present an evaluation of accelerating fault simulation by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is fre...
Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, K...
ESOP
2007
Springer
14 years 3 months ago
Cost Analysis of Java Bytecode
Abstract. Cost analysis of Java bytecode is complicated by its unstructured control flow, the use of an operand stack and its object-oriented programming features (like dynamic di...
Elvira Albert, Puri Arenas, Samir Genaim, Germ&aac...