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» Simulation of Soliton Circuits
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ISPD
2003
ACM
103views Hardware» more  ISPD 2003»
14 years 26 days ago
An integrated floorplanning with an efficient buffer planning algorithm
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, ...
EVOW
2003
Springer
14 years 25 days ago
GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages
Evolutionary Algorithms (EAs) have been proposed as a very powerful heuristic optimization technique to solve complex problems. Many case studies have shown that they work very eff...
Rolf Drechsler, Nicole Drechsler
3DIC
2009
IEEE
106views Hardware» more  3DIC 2009»
14 years 21 days ago
Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories
This paper investigates the effect of the TSV resistance (RTSV) on the performance of boost converters for Solid State Drive (SSD) using circuit simulation. When RTSV is 0Ω, both ...
Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, ...
DATE
2010
IEEE
132views Hardware» more  DATE 2010»
14 years 21 days ago
Programmable aging sensor for automotive safety-critical applications
- Electronic systems for safety-critical automotive applications must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while...
Julio César Vázquez, Víctor H...
APCCAS
2002
IEEE
138views Hardware» more  APCCAS 2002»
14 years 17 days ago
A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter
This paper presents a 10-bit pipeline ADC using double sampling technique to achieve a conversion rate of 40 MS/s at 2.5-V supply. The opamps are two-stage with folded-cascode as ...
A. Tamtrakarn, N. Wongkomet