1304 search results - page 30 / 261 » Simulation of Soliton Circuits |
ICCAD
1994
IEEE
14 years 26 days ago
1994
IEEE
We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
ASPDAC
1995
ACM
14 years 9 days ago
1995
ACM
: CMOS circuits have significant amounts of dynamic short-circuit (or through) current. This can be as large as 20% of the total in well-designed circuits, and up to 80% of the tot...
DSD
2010
IEEE
13 years 9 months ago
2010
IEEE
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...
NN
2008
Springer
13 years 8 months ago
2008
Springer
A silicon neuron circuit that produces spiking and bursting firing patterns, with biologically plausible spike shape, is presented. The circuit mimics the behaviour of known class...
MTV
2007
IEEE
14 years 3 months ago
2007
IEEE
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...