We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
: CMOS circuits have significant amounts of dynamic short-circuit (or through) current. This can be as large as 20% of the total in well-designed circuits, and up to 80% of the tot...
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...
A silicon neuron circuit that produces spiking and bursting firing patterns, with biologically plausible spike shape, is presented. The circuit mimics the behaviour of known class...
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...