17 search results - page 1 / 4 » Simultaneous Wire Sizing and Wire Spacing in Post-Layout Per... |
ASPDAC
1998
ACM
14 years 9 months ago
1998
ACM
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
ISCAS
2006
IEEE
14 years 11 months ago
2006
IEEE
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...
ICCAD
1994
IEEE
14 years 9 months ago
1994
IEEE
In this paper, we study the simultaneousdriver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipat...
ISLPED
1996
ACM
14 years 9 months ago
1996
ACM
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...
ICCD
2001
IEEE
15 years 2 months ago
2001
IEEE
As the operating frequency increases to Giga Hertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a line, it is necessary to consider the...