71 search results - page 12 / 15 » Snug set-associative caches: reducing leakage power while im... |
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Code compression has been shown to be an effective technique to reduce code size in memory constrained embedded systems. It has also been used as a way to increase cache hit ratio...
GLVLSI
2010
IEEE
14 years 23 days ago
2010
IEEE
The development of compiler-based mechanisms to reduce the percentage of hotspots and optimize the thermal profile of large register files has become an important issue. Thermal...