71 search results - page 6 / 15 » Snug set-associative caches: reducing leakage power while im... |
DAC
2004
ACM
14 years 8 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
ISCA
2012
IEEE
11 years 10 months ago
2012
IEEE
Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the...
CODES
2001
IEEE
13 years 11 months ago
2001
IEEE
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...