155 search results - page 29 / 31 » Soft delay error analysis in logic circuits |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
It has been widely recognized that the dynamic range information of an application can be exploited to reduce the datapath bitwidth of either processors or ASICs, and therefore th...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...