55 search results - page 6 / 11 » Software-based self-test of processors under power constrain... |
DAC
1997
ACM
13 years 11 months ago
1997
ACM
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
CF
2010
ACM
14 years 14 days ago
2010
ACM
As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to des...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Application-specific customization of the instruction set helps embedded processors achieve significant performance and power efficiency. In this paper, we explore customizatio...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...