122 search results - page 9 / 25 » Speculative Parallel Threading Architecture and Compilation |
ISCA
1998
IEEE
13 years 12 months ago
1998
IEEE
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
With the right techniques, multicore architectures may be able to continue the exponential performance trend that elevated the performance of applications of all types for decades...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
Task-selection policies are critical to the performance of any architecture that uses speculation to extract parallel tasks from a sequential thread. This paper demonstrates that ...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
Chip Multiprocessors (CMPs) are flexible, high-frequency platforms on which to support Thread-Level Speculation (TLS). However, for TLS to deliver on its promise, CMPs must explo...