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» Static Energy Reduction Techniques for Microprocessor Caches
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ICCD
2007
IEEE
100views Hardware» more  ICCD 2007»
14 years 4 months ago
VOSCH: Voltage scaled cache hierarchies
The cache hierarchy of state-of-the-art—especially multicore—microprocessors consumes a significant amount of area and energy. A significant amount of research has been devo...
Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li
HPCA
2006
IEEE
14 years 8 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
ISLPED
2006
ACM
119views Hardware» more  ISLPED 2006»
14 years 1 months ago
Process variation aware cache leakage management
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Ke Meng, Russ Joseph
PATMOS
2007
Springer
14 years 1 months ago
Exploiting Input Variations for Energy Reduction
The deep submicron semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions should go ...
Toshinori Sato, Yuji Kunitake
ICCD
2005
IEEE
109views Hardware» more  ICCD 2005»
14 years 4 months ago
Reducing the Energy of Speculative Instruction Schedulers
Energy dissipation from the issue queue and register file constitutes a large portion of the overall energy budget of an aggressive dynamically scheduled microprocessor. We propo...
Yongxiang Liu, Gokhan Memik, Glenn Reinman