651 search results - page 24 / 131 » Statistical Approach to NoC Design |
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock t...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
ICML
2003
IEEE
14 years 8 months ago
2003
IEEE
We investigate how stack filter function classes like weighted order statistics can be applied to classification problems. This leads to a new design criteria for linear classifie...
FPL
2005
Springer
14 years 1 months ago
2005
Springer
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...