306 search results - page 18 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
VTS
2005
IEEE
14 years 2 months ago
2005
IEEE
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new lat...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Metallic Carbon Nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs), causing excessive leakage, degraded noise margin and delay variat...
ICCAD
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
ISSS
1998
IEEE
14 years 20 days ago
1998
IEEE
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...