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TCAD
1998
127views more  TCAD 1998»
13 years 7 months ago
Gate-level power estimation using tagged probabilistic simulation
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
Chih-Shun Ding, Chi-Ying Tsui, Massoud Pedram
ISLPED
1997
ACM
106views Hardware» more  ISLPED 1997»
13 years 11 months ago
Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition
Significand pre-alignment is a pre requisite for floating point additions. This paper1 addresses the architectural design and energy delay evaluation of a Low Power Barrel Switch ...
R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Kha...
DATE
2010
IEEE
171views Hardware» more  DATE 2010»
14 years 22 days ago
Digital statistical analysis using VHDL
—Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects...
Manfred Dietrich, Uwe Eichler, Joachim Haase
ISLPED
2000
ACM
91views Hardware» more  ISLPED 2000»
14 years 1 hour ago
New clock-gating techniques for low-power flip-flops
Two novel low power flip-flops are presented in the paper. Proposed flip-flops use new gating techniques that reduce power dissipation deactivating the clock signal. Presented cir...
Antonio G. M. Strollo, E. Napoli, Davide De Caro
DAC
2003
ACM
14 years 27 days ago
Crosstalk noise in FPGAs
In recent years, due to rapid advances in VLSI manufacturing technology capable of packing more and more devices and wires on a chip, crosstalk has emerged as a serious problem af...
Yajun Ran, Malgorzata Marek-Sadowska