61 search results - page 6 / 13 » Statistical Leakage and Timing Optimization for Submicron Pr... |
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper we propose a new metric called “effective tunneling capacitance” (Ct eff ) to quantify the transient swing in the gate leakage (gate oxide tunneling) current ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...