We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Salu...
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...