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DAC
2010
ACM
13 years 10 months ago
Toward efficient large-scale performance modeling of integrated circuits via multi-mode/multi-corner sparse regression
In this paper, we propose a novel multi-mode/multi-corner sparse regression (MSR) algorithm to build large-scale performance models of integrated circuits at multiple working mode...
Wangyang Zhang, Tsung-Hao Chen, Ming Yuan Ting, Xi...
ICONIP
2007
13 years 11 months ago
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning
We proposed a neural segmentation model that is suitable for implementation in analog VLSIs using conventional CMOS technology. The model consists of neural oscillators mutually co...
Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asa...
ISLPED
2004
ACM
107views Hardware» more  ISLPED 2004»
14 years 3 months ago
Characterizing and modeling minimum energy operation for subthreshold circuits
Subthreshold operation is emerging as an energy-saving approach to many new applications. This paper examines energy minimization for circuits operating in the subthreshold region...
Benton H. Calhoun, Anantha Chandrakasan
VTS
2003
IEEE
119views Hardware» more  VTS 2003»
14 years 3 months ago
A Circuit Level Fault Model for Resistive Opens and Bridges
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. ...
ATVA
2007
Springer
150views Hardware» more  ATVA 2007»
14 years 2 months ago
3-Valued Circuit SAT for STE with Automatic Refinement
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
Orna Grumberg, Assaf Schuster, Avi Yadgar