871 search results - page 4 / 175 » Streaming Reduction Circuit |
ASPDAC
2007
ACM
14 years 1 months ago
2007
ACM
A new graph reduction approach to symbolic circuit analysis is developed in this paper. A Binary Decision Diagram (BDD) mechanism is formulated, together with a specially designed ...
ISSS
1995
IEEE
14 years 1 months ago
1995
IEEE
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
ICCAD
2004
IEEE
14 years 6 months ago
2004
IEEE
Abstract— This paper presents a post-route, timingconstrained gate-sizing algorithm for crosstalk reduction. Gate-sizing has emerged as a practical and feasible method to reduce ...
DATE
1998
IEEE
14 years 2 months ago
1998
IEEE
The power dissipated by system-level buses is the largest contribution to the global power of complex VLSI circuits. Therefore, the minimization of the switching activity at the I...
ISCC
2007
IEEE
14 years 4 months ago
2007
IEEE
This work presents the design of real-time applications for wireless sensor networks (WSNs) by using an algorithm based on data stream to process the sensor data. The proposed alg...