871 search results - page 57 / 175 » Streaming Reduction Circuit |
ISQED
2007
IEEE
14 years 4 months ago
2007
IEEE
The deep submicron (DSM) semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions sho...
ISQED
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper studies multi-dimensional optimization at both circuit and micro-architecture levels. By formulating and solving the optimization problem with conflicting design objec...
DAC
1999
ACM
14 years 2 months ago
1999
ACM
: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....
ISCAS
2006
IEEE
14 years 4 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
ICCAD
2005
IEEE
14 years 3 months ago
2005
IEEE
Suppression of leakage current and reduction in device-todevice variability will be key challenges for sub-45nm CMOS technologies. Non-classical transistor structures such as the ...