871 search results - page 66 / 175 » Streaming Reduction Circuit |
ISMVL
1997
IEEE
14 years 2 months ago
1997
IEEE
This paper shows how the application of a CMOS ternary logic is useful in the realisation of Delay Insensitive (01)asynchronous circuits. It is shown that fully DIasynchronous cir...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
Interconnect with an insufficient width may be subject to electromigration and eventually cause the failure of the circuit at any time during its lifetime. This problem has gotten...
NANONET
2009
Springer
14 years 4 months ago
2009
Springer
The Suspended Gate Field Effect Transistor (SG-FET) appears to have the potential to replace traditional FETs in sleep mode circuits, due to its abrupt switching enabled by electro...
ISQED
2005
IEEE
14 years 3 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...