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DAC
2006
ACM
14 years 10 months ago
MARS-C: modeling and reduction of soft errors in combinational circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
Natasa Miskov-Zivanov, Diana Marculescu
DATE
2005
IEEE
140views Hardware» more  DATE 2005»
14 years 3 months ago
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switc...
Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami,...
DATE
2004
IEEE
157views Hardware» more  DATE 2004»
14 years 1 months ago
Hierarchical Modeling and Simulation of Large Analog Circuits
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...
Sheldon X.-D. Tan, Zhenyu Qi, Hang Li
ASPDAC
2005
ACM
118views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
This paper proposes a novel wideband modeling technique for high-performance RF passives and linear(ized) analog circuits. The new method is based on a recently proposed sdomain h...
Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He
ET
2002
64views more  ET 2002»
13 years 9 months ago
Structural Fault Based Specification Reduction for Testing Analog Circuits
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is prop...
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen