Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ...
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srin...
— The dominant substrate noise coupling mechanism is determined for multiple switching gates based on a physically intuitive model. The model exhibits reasonable accuracy as comp...
Emre Salman, Eby G. Friedman, Radu M. Secareanu, O...
Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: t...
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...