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IOLTS
2006
IEEE
84views Hardware» more  IOLTS 2006»
14 years 2 months ago
An Improved Technique for Reducing False Alarms Due to Soft Errors
A significant fraction of soft errors in modern microprocessors has been reported to never lead to a system failure. Any concurrent error detection scheme that raises alarm every ...
Sandip Kundu, Ilia Polian
DATE
2005
IEEE
180views Hardware» more  DATE 2005»
14 years 2 months ago
A Coprocessor for Accelerating Visual Information Processing
Visual information processing will play an increasingly important role in future electronics systems. In many applications, e.g. video surveillance cameras, data throughput of mic...
Walter Stechele, L. Alvado Cárcel, Stephan ...
LCTRTS
2007
Springer
14 years 3 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
ICCAD
2008
IEEE
153views Hardware» more  ICCAD 2008»
14 years 5 months ago
SPM management using Markov chain based data access prediction
— Leveraging the power of scratchpad memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular a...
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kan...
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
14 years 2 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...