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EURODAC
1995
IEEE
198views VHDL» more  EURODAC 1995»
14 years 4 days ago
On generating compact test sequences for synchronous sequential circuits
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
Irith Pomeranz, Sudhakar M. Reddy
ASPDAC
2004
ACM
79views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Preserving synchronizing sequences of sequential circuits after retiming
Abstract We propose a novel approach to preserve the synchronizing sequences of a circuit after retiming. The significance of this problem stems from the necessity of maintaining c...
Maher N. Mneimneh, Karem A. Sakallah, John Moondan...
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
14 years 1 months ago
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies
Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CE...
Thomas Verdel, Yiorgos Makris
SBCCI
2003
ACM
115views VLSI» more  SBCCI 2003»
14 years 1 months ago
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling all...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
14 years 24 days ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy