82 search results - page 11 / 17 » Synthesis of High Performance Low Power Dynamic CMOS Circuit... |
153
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GLVLSI
2010
IEEE
15 years 8 months ago
2010
IEEE
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
133
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ASPDAC
2006
ACM
15 years 9 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
127
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ISCAS
2008
IEEE
15 years 10 months ago
2008
IEEE
Abstract— This paper presents circuits that enable dynamic voltage and frequency scaling (DVFS) for finegrained chip multi-processors to reduce both dynamic and leakage power di...
117
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ICCD
2003
IEEE
16 years 12 days ago
2003
IEEE
- This paper presents a precomputation-based guarding technique to reduce both dynamic and static power consumptions in CMOS VLSI circuits. More precisely, a high threshold sleep t...
102
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ISCAS
2005
IEEE
15 years 9 months ago
2005
IEEE
—This paper presents a 2GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Nonlinear current steering digital to analog converter (DAC) has been utilized to con...