87 search results - page 1 / 18 » Synthesis of Testable RTL Designs |
VLSID
1998
IEEE
14 years 3 months ago
1998
IEEE
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
VLSID
2004
IEEE
14 years 11 months ago
2004
IEEE
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
ICCAD
2002
IEEE
14 years 7 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
ASPDAC
1995
ACM
14 years 2 months ago
1995
ACM
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
DFT
1998
IEEE
14 years 3 months ago
1998
IEEE
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...