419 search results - page 10 / 84 » Synthesis of networks on chips for 3D systems on chips |
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
VLSID
2010
IEEE
14 years 14 days ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
SLIP
2009
ACM
14 years 3 months ago
2009
ACM
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
ISCAS
2006
IEEE
2006
IEEE
Microelectromechanical systems in 3D SOI-CMOS: sensing electronics embedded in mechanical structures
14 years 2 months ago
— We discuss the design of CMOS MEMS in a 3D SOI-CMOS technology. We present layout architectures, preliminary mechanics modeling using finite element analysis and release proce...