121 search results - page 7 / 25 » System-level power optimization: techniques and tools |
DAC
2004
ACM
14 years 9 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
SOFSEM
2000
Springer
13 years 11 months ago
2000
Springer
For half a century since computers came into existence, the goal of finding elegant and efficient algorithms to solve "simple" (welldefined and well-structured) problems ...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
This paper presents a novel repeater insertion algorithm for the power minimization of realistic interconnect trees under given timing budgets. Our algorithm judiciously combines ...