82 search results - page 13 / 17 » SystemC transaction level models and RTL verification |
DATE
2003
IEEE
14 years 25 days ago
2003
IEEE
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
ISSS
2002
IEEE
14 years 14 days ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
FDL
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents an approach for modeling an inertial navigation system. This system consists of a 3D acceleration and rotation sensor array, analog and digital error correctio...