8 search results - page 1 / 2 » TAM Optimization for Mixed-Signal SOCs using Analog Test Wra... |
ICCAD
2003
IEEE
14 years 7 months ago
2003
IEEE
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
DATE
2005
IEEE
14 years 4 months ago
2005
IEEE
Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prio...
ICCD
2005
IEEE
14 years 7 months ago
2005
IEEE
The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog ...
ET
2002
13 years 10 months ago
2002
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
VTS
2002
IEEE
14 years 3 months ago
2002
IEEE
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...