3340 search results - page 133 / 668 » Teaching networking hardware |
DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper presents a new approach that allows remote testing and diagnosis of complex (Systems-on-Chip) and embedded IP cores. The approach extends both on-chip design-for-test (...
114
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DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
This paper presents a new technique for automatically creating analog circuit models. The method extracts - from trained neural networks - piecewise linear models expressing the l...
98
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FPL
2003
Springer
15 years 9 months ago
2003
Springer
This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The netw...
131
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ICCAD
1998
IEEE
15 years 8 months ago
1998
IEEE
In this paper, an approach to symbolic model checking of process networks is introduced. It is based on interval decision diagrams (IDDs), a representation of multi-valued functio...
132
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ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
Abstract— In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and ...