15 search results - page 1 / 3 » Test Compaction for Synchronous Sequential Circuits by Test ... |
GLVLSI
1998
IEEE
14 years 25 days ago
1998
IEEE
EURODAC
1995
IEEE
14 years 3 days ago
1995
IEEE
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test applic...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficien...
ATS
1998
IEEE
14 years 25 days ago
1998
IEEE
We propose a new static test set compaction method based on a careful examination of attributes of fault coverage curves. Our method is based on two key ideas: 1 fault-list and te...
ICCAD
1999
IEEE
14 years 26 days ago
1999
IEEE
We describe a method referred to as sequence counting to improve on the levels of compaction achievable by vector omission based static compaction procedures. Such procedures are ...