203 search results - page 12 / 41 » Test Generation and Fault Localization for Quantum Circuits |
DATE
1998
IEEE
13 years 11 months ago
1998
IEEE
A new approach for sequential circuit test generation is proposed that combines software testing based techniques at the high level with test enhancement techniques at the gate le...
DATE
1997
IEEE
13 years 11 months ago
1997
IEEE
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability id...