203 search results - page 13 / 41 » Test Generation and Fault Localization for Quantum Circuits |
119
Voted
DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
116
click to vote
ICCAD
2000
IEEE
15 years 7 months ago
2000
IEEE
In this paper, we propose a novel fault-oriented test generation methodology for detection and isolation of faults in analog circuits. Given the description of the circuit-underte...
129
click to vote
ICCAD
1997
IEEE
15 years 7 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
116
Voted
ICCD
2006
IEEE
16 years 11 days ago
2006
IEEE
— We have entered an era where chip yields are decreasing with scaling. A new concept called intelligible testing has been previously proposed with the goal of reversing this tre...
129
Voted
DFT
2003
IEEE
15 years 8 months ago
2003
IEEE
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...