61 search results - page 3 / 13 » Test Pattern Generation Under Low Power Constraints |
DATE
2010
IEEE
14 years 21 days ago
2010
IEEE
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
ATS
2009
IEEE
14 years 2 months ago
2009
IEEE
—Measuring the steady state leakage current (IDDQ) is very successful in detecting faults not discovered by standard fault models. But vector dependencies of IDDQ decrease the re...
CDC
2010
IEEE
13 years 2 months ago
2010
IEEE
This paper is concerned with studying how the minimum power loss in a power system is related to its network topology. The existing algorithms in the literature all exploit nonline...