22 search results - page 1 / 5 » Test Volume and Application Time Reduction Through Scan Chai... |
DAC
2001
ACM
14 years 11 months ago
2001
ACM
DAC
2003
ACM
14 years 4 months ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
DFT
2002
IEEE
14 years 3 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
ITC
2002
IEEE
14 years 3 months ago
2002
IEEE
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
VTS
2003
IEEE
14 years 4 months ago
2003
IEEE
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...