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» Test generation in VLSI circuits for crosstalk noise
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ISCAS
2002
IEEE
195views Hardware» more  ISCAS 2002»
14 years 16 days ago
A low-power, low-noise CMOS amplifier for neural recording applications
There is a need among scientists and clinicians for lownoise, low-power biosignal amplifiers capable of amplifying signals in the mHz to kHz range while rejecting large dc offsets...
Reid R. Harrison
ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
13 years 12 months ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz
VTS
2008
IEEE
119views Hardware» more  VTS 2008»
14 years 2 months ago
Error Sequence Analysis
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
Jaekwang Lee, Intaik Park, Edward J. McCluskey
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
13 years 11 months ago
Cycle-accurate macro-models for RT-level power analysis
 In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding
VLSID
2008
IEEE
117views VLSI» more  VLSID 2008»
14 years 8 months ago
Single Event Upset: An Embedded Tutorial
Abstract-- With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends su...
Fan Wang, Vishwani D. Agrawal