64 search results - page 3 / 13 » Test pattern generation for width compression in BIST |
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
DELTA
2008
IEEE
14 years 1 months ago
2008
IEEE
Re-using embedded resources for implementing builtin self test mechanisms allows test cost reduction. In this paper we demonstrate how to implement costefficient built-in self tes...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
—A Built-In Self-Test (BIST) approach for functionality measurements, including noise figure (NF), linearity and frequency response of analog circuitry in mixedsignal systems, is...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...