64 search results - page 5 / 13 » Test pattern generation for width compression in BIST |
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
ICCAD
1995
IEEE
14 years 4 days ago
1995
IEEE
Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic ...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
DATE
1999
IEEE
14 years 27 days ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
VLSID
2001
IEEE
14 years 9 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...