72 search results - page 4 / 15 » Test register insertion with minimum hardware cost |
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
ET
2002
13 years 7 months ago
2002
In this paper we explore two alternative approaches to system diagnosis. The first strategy is based on testability analysis performed by SATAN tool. The second approach performed ...
FPGA
2010
ACM
14 years 1 months ago
2010
ACM
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
AADEBUG
2005
Springer
14 years 1 months ago
2005
Springer
Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the u...