244 search results - page 7 / 49 » Testing Digital Circuits with Constraints |
EVOW
1999
Springer
14 years 26 days ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
FDTC
2010
Springer
13 years 6 months ago
2010
Springer
The testability of the cryptographic cores brings in an extra dimension to the process of digital circuits testing
DATE
1999
IEEE
14 years 28 days ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
VLSID
2007
IEEE
14 years 9 months ago
2007
IEEE
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...