244 search results - page 9 / 49 » Testing Digital Circuits with Constraints |
ISQED
2009
IEEE
14 years 3 months ago
2009
IEEE
— With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efï¬...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...
DATE
2000
IEEE
14 years 1 months ago
2000
IEEE
An objective of DSP testing should be to ensure that any errors due to missed faults are infrequent compared to a circuit’s intrinsic errors, such as overflow. A method is prop...
DFT
2004
IEEE
14 years 10 days ago
2004
IEEE
In this paper we analyze the performance of a mixed built-in-self-test (BiST) for RF IC digital transceivers, where a baseband processor can be used both as a test pattern generat...
ETS
2009
IEEE
13 years 6 months ago
2009
IEEE
This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both ...