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ISLPED
2000
ACM
115views Hardware» more  ISLPED 2000»
13 years 11 months ago
Model and analysis for combined package and on-chip power grid simulation
We present new modeling and simulation techniques to improve the accuracy and efficiency of transient analysis of large power distribution grids. These include an accurate model ...
Rajendran Panda, David Blaauw, Rajat Chaudhry, Vla...
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
14 years 29 days ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
ICCAD
2009
IEEE
89views Hardware» more  ICCAD 2009»
13 years 5 months ago
Decoupling capacitance efficient placement for reducing transient power supply noise
Decoupling capacitance (decap) is an efficient way to reduce transient noise in on-chip power supply networks. However, excessive decap may cause more leakage power, chip resource...
Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. T...
CODES
2006
IEEE
14 years 1 months ago
Thermal-aware high-level synthesis based on network flow method
Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reli...
Pilok Lim, Taewhan Kim
ISPD
1999
ACM
106views Hardware» more  ISPD 1999»
13 years 11 months ago
Timing driven maze routing
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
Sung-Woo Hur, Ashok Jagannathan, John Lillis