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ASPDAC
2009
ACM
159views Hardware» more  ASPDAC 2009»
14 years 1 months ago
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapa...
NOCS
2010
IEEE
13 years 6 months ago
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs
The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an importan...
Chia-Hsin Owen Chen, Niket Agarwal, Tushar Krishna...
DAC
1994
ACM
14 years 16 days ago
Minimal Delay Interconnect Design Using Alphabetic Trees
Abstract - We propose a new algorithm for the performancedriven interconnect design problem, based on alphabetic trees. The interconnect topology is determined in a global manner a...
Ashok Vittal, Malgorzata Marek-Sadowska
ALGORITHMICA
2008
110views more  ALGORITHMICA 2008»
13 years 8 months ago
Bandwidth-Constrained Allocation in Grid Computing
Grid computing systems pool together the resources of many workstations to create a virtual computing reservoir. Users can "draw" resources using a pay-as-you-go model, c...
Anshul Kothari, Subhash Suri, Yunhong Zhou
ICCAD
1996
IEEE
129views Hardware» more  ICCAD 1996»
14 years 18 days ago
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits
-- In this tutorial we discuss concepts and techniques for the accurate and efficient modeling and extraction of interconnect parasitics in VLSI designs. Due toincreasing operating...
N. P. van der Meijs, T. Smedes