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FPL
2007
Springer
98views Hardware» more  FPL 2007»
15 years 4 months ago
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel ...
Shannon Koh, Oliver Diessel
QUESTA
2006
87views more  QUESTA 2006»
15 years 2 months ago
Mean value analysis for polling systems
The present paper deals with the problem of calculating mean delays in polling systems with either exhaustive or gated service. We develop a mean value analysis (MVA) to compute t...
Erik M. M. Winands, Ivo J. B. F. Adan, G. J. van H...
159
Voted
COR
2008
142views more  COR 2008»
15 years 2 months ago
Modeling and solving the rooted distance-constrained minimum spanning tree problem
In this paper we discuss models and methods for solving the rooted distance constrained minimum spanning tree problem which is defined as follows: given a graph G = (V, E) with no...
Luis Gouveia, Ana Paias, Dushyant Sharma
123
Voted
INFOCOM
2000
IEEE
15 years 7 months ago
QoS Routing with Performance-Dependent Costs
Abstract—We study a network model in which each network link is associated with a set of delays and costs. These costs are a function of the delays and reflect the prices paid i...
Funda Ergün, Rakesh K. Sinha, Lisa Zhang
ICCAD
1996
IEEE
114views Hardware» more  ICCAD 1996»
15 years 6 months ago
An efficient approach to simultaneous transistor and interconnect sizing
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We de ne a class of optimization problems as CH-posynomial programs and reveal a genera...
Jason Cong, Lei He