225 search results - page 2 / 45 » The Design and Optimization of SOC Test Solutions |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
VTS
2003
IEEE
14 years 21 days ago
2003
IEEE
Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimizati...
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...