Sciweavers

2424 search results - page 101 / 485
» The High Level Architecture for Simulations
Sort
View
DATE
2010
IEEE
105views Hardware» more  DATE 2010»
14 years 1 months ago
Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs
Abstract—We present a set of modeling constructs accompanied by a high performance simulation kernel for accuracy adaptive transaction level models. In contrast to traditional, ...
Rauf Salimi Khaligh, Martin Radetzki
NETWORK
2007
145views more  NETWORK 2007»
13 years 8 months ago
Analysis of Shared Memory Priority Queues with Two Discard Levels
— Two rate SLAs become increasingly popular in today’s Internet, allowing a customer to save money by paying one price for committed traffic and a much lower price for additio...
Shlomi Bergida, Yuval Shavitt
DATE
2004
IEEE
146views Hardware» more  DATE 2004»
14 years 18 days ago
Analyzing On-Chip Communication in a MPSoC Environment
This work focuses on communication architecture analysis for multi-processor Systems-on-Chips (MPSoCs), and it leverages a SystemC-based platform to simulate a complete multi-proc...
Mirko Loghi, Federico Angiolini, Davide Bertozzi, ...
CODES
2005
IEEE
14 years 2 months ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
CODES
2004
IEEE
14 years 18 days ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...